Introduction
A modern processor chip contains tens of billions of transistors on a piece of silicon roughly the size of a fingernail. The smallest features on that chip are a few nanometres wide, which is smaller than most viruses and only a few dozen silicon atoms across.
Here is the part that makes it genuinely difficult. Those features are printed using light, and the light used has a wavelength longer than the features it creates.
Printing something smaller than your own wavelength is a bit like painting a line thinner than your brush, and the engineering required to do it reliably, billions of times per chip, is arguably the most advanced manufacturing humanity has achieved.
There is also the matter of cleanliness. A single dust particle landing in the wrong place destroys a die. Semiconductor fabs therefore operate at particle levels thousands of times cleaner than a hospital operating theatre.
For electronics, mechanical, chemical and materials engineering students, this topic is worth learning now. India is building its first commercial fabrication and packaging facilities under national semiconductor programmes, and the sector will need engineers who understand the process rather than only the device physics.
What Is the Semiconductor Manufacturing Process?
The semiconductor manufacturing process is the sequence of converting purified silicon into integrated circuits by building transistor structures layer by layer on a wafer, then testing, separating and packaging the individual chips.
The whole industry divides into three stages, and separating them clearly is the first step to understanding the subject.
Front end of line, often shortened to FEOL, builds the transistors themselves on the silicon surface.
Back end of line, or BEOL, builds the metal wiring layers that connect those transistors into circuits.
Assembly, packaging and test, sometimes called OSAT for outsourced semiconductor assembly and test, separates the wafer into individual dies and packages each one into a usable component.
A useful commercial distinction to know. A foundry manufactures chips designed by other companies, a fabless company designs chips but owns no factory, and an IDM, meaning integrated device manufacturer, does both.
The core idea in one sentence. Semiconductor manufacturing is not a single process but the repetition of a small set of steps, deposit, pattern, etch and dope, several hundred times over, each cycle adding one more layer of the structure.
Simple definition for your exam: The semiconductor manufacturing process is the fabrication of integrated circuits through repeated cycles of thin film deposition, photolithographic patterning, etching, doping and planarisation on a silicon wafer, followed by wafer testing, dicing, packaging and final testing.
From Sand to Silicon Wafer
Everything begins with ordinary silica sand, but the purification required is extreme.
Metallurgical grade silicon is produced first by reducing silica with carbon in an electric arc furnace, giving silicon around 98 to 99 percent pure. That sounds high but is nowhere near sufficient.
Electronic grade silicon is produced by the Siemens process, where silicon is converted to trichlorosilane gas, purified by distillation and then deposited back as ultra pure polysilicon. The result reaches roughly eleven nines purity, meaning 99.999999999 percent. To put that in perspective, it allows fewer than one foreign atom per billion silicon atoms.
Crystal growth uses the Czochralski process. Polysilicon is melted in a crucible, a small seed crystal is dipped into the melt and slowly rotated and withdrawn. The melt solidifies onto the seed following its crystal orientation, growing a single crystal cylinder called an ingot that can be 300 millimetres in diameter and two metres long, weighing hundreds of kilograms.
Why single crystal matters. Grain boundaries in a polycrystalline material would disrupt the regular atomic lattice and scatter charge carriers, making predictable transistor behaviour impossible. The entire wafer must be one continuous crystal.
Wafer slicing cuts the ingot into thin discs using a wire saw, typically 0.7 to 0.8 millimetres thick.
Lapping, etching and polishing follow, ending with chemical mechanical polishing to produce a surface flat to within a few nanometres across the whole 300 millimetre wafer. Any deviation would put part of the wafer out of focus during lithography.
Wafer size economics are worth understanding. Larger wafers yield more dies per process run, so cost per chip falls. The industry moved from 150 to 200 to 300 millimetres, and a transition to 450 millimetres was studied but stalled because the tooling cost proved prohibitive.
The Semiconductor Manufacturing Process Step by Step
The wafer now enters the fab, where it will undergo several hundred process steps over several weeks or months. The sequence below is repeated many times, once for each layer of the device.
Step 1: Oxidation
The wafer is heated in a furnace with oxygen or steam, growing a thin layer of silicon dioxide on the surface. This oxide serves as an electrical insulator, a masking layer during doping and, in the transistor itself, the gate dielectric.
Step 2: Deposition
Thin films of conductor, insulator or semiconductor material are added to the surface.
Chemical vapour deposition, or CVD, reacts gases at the wafer surface to form a solid film. Variants include low pressure CVD and plasma enhanced CVD for lower temperature processing.
Physical vapour deposition, or PVD, uses sputtering, where energetic ions knock atoms from a target that then land on the wafer. It is widely used for metals.
Atomic layer deposition, or ALD, builds the film one atomic layer at a time using self limiting surface reactions. It gives extraordinary thickness control and conformal coverage, which becomes essential at very small feature sizes.
Epitaxy grows a crystalline layer that continues the lattice of the wafer beneath it.
Step 3: Photolithography
This is the patterning step and the heart of the entire process, covered in detail in the next section.
Step 4: Etching
Material is removed where the pattern dictates.
Wet etching uses liquid chemicals. It is simple and cheap but isotropic, meaning it etches sideways as well as downward, which undercuts the mask and limits how small features can be.
Dry etching, mainly reactive ion etching, uses a plasma. It is anisotropic, etching almost straight down with very little lateral attack, which is why it dominates modern fabrication.
Selectivity is the key parameter, meaning the etch must remove the target material much faster than the mask or the layer beneath it.
Step 5: Doping
Doping introduces impurity atoms to change the electrical character of the silicon, creating the n type and p type regions that make a transistor work.
Ion implantation is the standard method. Dopant ions are accelerated to high energy and fired into the silicon, giving precise control over both dose and depth.
Diffusion uses high temperature to drive dopants in from the surface, an older method still used for some applications.
Annealing follows implantation. The high energy ions damage the crystal lattice, so the wafer is heated, often by rapid thermal annealing, to repair the damage and activate the dopants by moving them into lattice positions.
Common dopants are boron for p type, since it has one fewer valence electron than silicon, and phosphorus or arsenic for n type, having one more.
Step 6: Chemical Mechanical Planarisation
After each set of layers, the surface becomes uneven. CMP polishes it flat using a rotating pad and an abrasive chemical slurry.
Why this matters more than it sounds. Photolithography has an extremely shallow depth of focus at small feature sizes. If the surface is not flat, part of the pattern is out of focus and prints incorrectly. Planarisation is what makes multilayer chips possible at all.
Step 7: Metallisation and Interconnect
Once transistors are built, they must be wired together. Modern chips use copper interconnect formed by the damascene process, where trenches are etched into an insulating layer, filled with copper by electroplating, and the excess removed by CMP.
Barrier layers of tantalum or tantalum nitride prevent copper from diffusing into the silicon, where it would destroy device performance.
Low k dielectrics are used between wires to reduce capacitance, because at these dimensions the delay caused by the wiring exceeds the switching delay of the transistors themselves.
A modern processor may have more than fifteen metal layers stacked above the transistors.
Step 8: Wafer Test
Every die is tested electrically on the wafer using fine probes, in a step called wafer sort or electrical die sorting. Failing dies are marked or recorded in a map so they are discarded after dicing rather than being packaged at cost.
Photolithography Process Steps Explained
Photolithography is where the circuit pattern is transferred onto the wafer, and it is repeated for every layer. It is also the step that determines how small the transistors can be, which is why it dominates the technology and the cost of a fab.
The sequence runs as follows.
Cleaning and priming prepares the wafer surface so the photoresist adheres properly.
Coating applies liquid photoresist by spinning the wafer at high speed, producing a uniform film typically under a micron thick.
Soft bake drives off solvent and firms up the resist.
Alignment and exposure is the critical step. A photomask or reticle carrying the pattern is aligned to the features already on the wafer, and light is projected through it onto the resist. Modern steppers and scanners project the pattern onto one small area at a time and then step across the wafer, repeating until the whole wafer is exposed.
Post exposure bake completes the chemical reaction in the resist.
Development dissolves away the exposed regions in a positive resist, or the unexposed regions in a negative resist, leaving the pattern standing in resist on the wafer.
Hard bake hardens the remaining pattern so it survives the etching or implantation that follows.
After the subsequent process step, the resist is stripped and the cycle begins again for the next layer.
Resolution and Why Wavelength Matters
The smallest feature that can be printed is governed by the Rayleigh criterion, which in simple terms says resolution improves with shorter wavelength and higher numerical aperture, and worsens with a larger process factor.
This is why the industry has pushed steadily to shorter wavelengths.
| Light source | Wavelength | Era of use |
|---|---|---|
| Mercury g line | 436 nm | Early lithography |
| Mercury i line | 365 nm | 1990s |
| KrF excimer laser | 248 nm | Deep ultraviolet |
| ArF excimer laser | 193 nm | Long dominant workhorse |
| ArF immersion | 193 nm effective improvement | Water between lens and wafer raises numerical aperture |
| EUV | 13.5 nm | Current leading edge nodes |
Immersion lithography was an elegant solution. Placing purified water between the final lens and the wafer increases the numerical aperture, improving resolution without changing the wavelength.
Multiple patterning extended 193 nm lithography further by splitting one dense pattern into two or more separate exposures. It works but multiplies cost and cycle time.
EUV lithography at 13.5 nanometres is the current frontier. It is extraordinarily difficult because EUV is absorbed by air and by glass, so the entire optical path must be in vacuum using mirrors rather than lenses, and the light itself is generated by firing lasers at droplets of molten tin. EUV machines are among the most expensive and complex tools ever built.
Process node names deserve a caution for students. Terms such as 7 nm or 3 nm no longer correspond to any physical dimension on the chip. They are marketing designations indicating a generation of technology, not a measured feature width. Examiners occasionally ask this, and knowing it signals genuine understanding.
Cleanroom Requirements in Semiconductor Fabs
Contamination control in a fab exceeds every other industry, and the reason is simple arithmetic. If a feature is 10 nanometres wide, a particle 100 nanometres across is ten times larger than the structure it lands on.
Cleanroom classification follows ISO 14644. Critical fab areas operate at ISO Class 1 to Class 3, permitting almost no particles above 0.1 micron per cubic metre. For comparison, a hospital operating theatre is roughly ISO Class 7.
How it is achieved. Air passes continuously through ULPA filters in the ceiling and flows downward in a laminar pattern through a perforated floor, with hundreds of air changes per hour. Personnel wear full bunny suits, and increasingly wafers travel in sealed FOUP carriers so they never contact room air at all.
Ultrapure water is used in enormous quantities for rinsing and CMP, purified far beyond drinking water standards to remove ions, organics and particles.
Vibration and temperature control are equally critical. Lithography tools require the building to be isolated from vibration, and temperature is held within a fraction of a degree because thermal expansion alone would misalign the pattern.
Chemical purity is controlled to parts per trillion for many process gases and chemicals.
The cost consequence. A leading edge fab now costs well over ten billion dollars, and a substantial share of that is the building and its environmental systems rather than the process tools themselves.
Packaging, Assembly and Final Test
Once wafer processing is complete, the chips must be turned into usable components. This stage is often carried out by specialist OSAT companies rather than the fab itself.
Wafer thinning grinds the back of the wafer down, since the bulk silicon is no longer needed and thinner packages are preferred.
Dicing separates the wafer into individual dies using a diamond blade saw or a laser, cutting along the scribe lines between dies.
Die attach bonds each good die onto a lead frame or package substrate using adhesive or solder.
Interconnection connects the die electrically to the package. Wire bonding uses fine gold or copper wires from pads on the die to the package leads. Flip chip instead places solder bumps directly on the die face and mounts it upside down onto the substrate, giving shorter connections and far more input and output points.
Encapsulation moulds epoxy compound around the die to protect it mechanically and environmentally.
Ball attach and marking completes the package, adding solder balls for board mounting and laser marking the part identification.
Final test exercises each packaged device electrically across its specified temperature range, sorting parts by speed and function. Burn in runs devices at elevated temperature and voltage to force early life failures to occur before shipment.
Advanced packaging has become one of the most important areas of the industry, because scaling transistors further is increasingly difficult and expensive.
System in package places several different dies in one package. 2.5D packaging places multiple dies side by side on a silicon interposer. 3D stacking stacks dies vertically connected by through silicon vias. Chiplets split a large design into smaller dies made on different process nodes and combine them in one package, improving yield and allowing each function to use the most suitable technology.
For students in India, this stage matters practically. ATMP and OSAT facilities require far less capital than a leading edge fab, which is why India’s semiconductor programme has attracted packaging and assembly investment first.
Yield, Cost and Why Chips Are Expensive
Yield is the defining economic metric of this industry, and understanding it explains almost everything about how chips are priced.
Yield is the percentage of dies on a wafer that function correctly. Because a wafer costs the same to process regardless of how many good dies it produces, yield determines cost per chip directly.
Defect density is the underlying driver. Randomly distributed defects mean that larger dies are more likely to contain at least one defect, so large chips such as high end processors and GPUs have inherently lower yield than small ones. This is a major reason chiplet designs have become attractive, since several small dies yield better than one large one.
Yield learning is a normal part of a new process. A node typically starts with poor yield that improves steadily over months and years as defect sources are identified and eliminated.
Binning makes commercial use of partial failures. Devices that fail to reach the top speed grade, or that have some cores non functional, are sold as lower specification products rather than scrapped. Many product tiers within a processor family come from the same wafer.
Cycle time in a fab is measured in weeks to months, with several hundred process steps and repeated queueing at expensive tools. That long pipeline is why the industry responds so slowly to demand changes, and it is a large part of why the global chip shortage persisted as long as it did.
Semiconductor Industry Structure and India’s Position
Foundries manufacture chips designed by others, with capacity concentrated heavily in a small number of companies and geographies.
Fabless companies design and sell chips while outsourcing all manufacturing.
IDMs design and manufacture their own products.
OSAT providers handle assembly, packaging and test.
Equipment and materials suppliers form a highly concentrated and strategically critical layer, since a small number of firms supply the lithography, deposition and etch tools that every fab requires.
India’s position. The country has long been strong in chip design, with a very large share of global semiconductor design engineering carried out here, but historically had no commercial fabrication. The India Semiconductor Mission and associated incentive schemes are now funding fabrication, display and ATMP facilities, with assembly and packaging plants progressing fastest because of their lower capital requirement.
For students, the practical implication is clear. Design roles have existed in India for decades and are competitive. Process, equipment and packaging engineering roles are the ones being created now, and the talent pool for them is far thinner.
Frequently Asked Questions (FAQs)
1. What is the semiconductor manufacturing process in simple words?
Purified silicon is grown into a single crystal and sliced into wafers.
Layers are then built up on the wafer by depositing material, printing patterns with light, etching away unwanted areas and adding dopants.
The cycle repeats hundreds of times, after which the wafer is tested, cut into individual chips and packaged.
2. How is a silicon wafer made?
Sand is reduced to metallurgical grade silicon, then purified to electronic grade by the Siemens process.
The purified silicon is melted and grown into a single crystal ingot by the Czochralski process, which is then sliced and polished into wafers.
3. What is photolithography?
It is the process of transferring a circuit pattern onto the wafer using light.
Photoresist is coated onto the wafer, exposed through a patterned photomask, and developed to leave the pattern that guides etching or doping.
4. Why does the industry use EUV lithography?
Because shorter wavelength allows smaller features to be printed.
EUV at 13.5 nanometres is far shorter than the 193 nanometres used previously, though it requires vacuum operation and mirror based optics because EUV is absorbed by air and glass.
5. What is the difference between wet etching and dry etching?
Wet etching uses liquid chemicals and is isotropic, meaning it etches sideways as well as downward.
Dry etching uses plasma and is anisotropic, etching almost straight down, which is why it is used for small features.
6. What is doping and why is it needed?
Doping adds impurity atoms such as boron or phosphorus to silicon.
It creates the p type and n type regions that make transistors function.
7. Why do semiconductor fabs need such extreme cleanrooms?
Because chip features are only a few nanometres wide, so even a sub micron particle is far larger than the structures it lands on and will destroy the die.
Critical fab areas operate at ISO Class 1 to 3, far cleaner than a hospital operating theatre.
8. What is yield and why does it matter?
Yield is the percentage of dies on a wafer that work correctly.
Since a wafer costs the same to process regardless of outcome, yield directly determines the cost of each working chip.
9. Does a 3 nm process mean the transistors are 3 nanometres wide?
No.
Modern node names are marketing designations for a technology generation and no longer correspond to any physical dimension on the chip.
10. What is the difference between a fab and an OSAT facility?
A fab manufactures the circuits on silicon wafers.
An OSAT facility performs assembly, packaging and testing, converting finished wafers into packaged chips, and requires far less capital investment than a fab.
Conclusion
Semiconductor manufacturing is the same handful of operations, deposit, pattern, etch and dope, repeated with extraordinary precision several hundred times on a single wafer. What makes it remarkable is not the individual step but the accumulated accuracy, because every one of those steps must align to the layers beneath it within a few nanometres.
For your exams, hold three anchors. The route from sand to wafer, including the Siemens process for purity and the Czochralski process for single crystal growth. The photolithography cycle in order, from coating through exposure, development and etching to resist strip. And the difference between wet and dry etching, since isotropic versus anisotropic behaviour is one of the most commonly examined points in this subject.
For your interviews, two answers signal real understanding. Explaining why chemical mechanical planarisation is essential, because lithography has almost no depth of focus at these dimensions, and explaining why larger dies have inherently lower yield, which is the reason chiplet architectures exist.
For your career, the timing in India is unusual. Design capability here is mature and competitive, while process, equipment and packaging expertise is scarce and being built from a low base. If you are willing to learn the manufacturing side rather than only the device physics, you will be entering a field where experienced people simply do not yet exist in sufficient numbers.